Technology
Neuromorphic Chips Mimicking Synaptic Plasticity
Quick fact
The human brain uses about 20 watts of power, while a conventional supercomputer simulating a fraction of its activity can consume megawatts. Neuromorphic chips aim to close that gap by copying the brain's efficient, event-driven processing.
Why this is interesting
Your brain learns by tweaking the strength of connections between neurons. What if a computer chip could do the same—rewiring itself with every experience?
Read the full explanation
Understanding Neuromorphic Chips Mimicking Synaptic Plasticity
Imagine a library where every time you read a book, the librarian physically moves it closer to your favorite chair, making it easier to reach next time. That's how synaptic plasticity works in the brain—connections between neurons that are used often become stronger, while unused ones weaken. Neuromorphic chips are computer hardware designed to perform this same trick. Instead of running software that calculates rules, these chips are built with physical components (like transistors or memristors) that act as artificial synapses. When a signal passes through, that synaptic component can change its state—like turning a dial to increase or decrease the flow. So, the chip's 'wiring' literally adapts based on the data it processes. This is a radical departure from traditional computers, where memory and processing are separate, and the program is fixed.
A deeper explanation
Synaptic plasticity in neuromorphic chips is implemented through a variety of device-level mechanisms that emulate biological learning rules. One prominent approach uses memristors—two-terminal devices whose conductance changes in response to applied voltage or current. In a typical setup, a voltage pulse across the memristor induces the migration of oxygen vacancies or the formation/rupture of a conductive filament, permanently altering resistance. This change mimics long-term potentiation (LTP) and long-term depression (LTD) of biological synapses. Other technologies include phase-change memory (PCM), where crystallinity changes modulate resistance, and ferroelectric transistors that switch polarization states. These devices are integrated into crossbar arrays, where each intersection corresponds to a synapse, enabling matrix-vector multiplications in the analog domain. Learning rules, such as spike-timing-dependent plasticity (STDP), are implemented by applying carefully timed pre- and postsynaptic spikes to the device, causing weight updates dependent on the time difference. The weight update is local and correlates with activity, mirroring Hebbian learning. Evidence of functionality comes from research demonstrations, such as IBM's TrueNorth and Intel's Loihi, which have shown significant energy reductions for specific tasks (e.g., pattern recognition) compared to conventional hardware. However, boundaries remain: current chips have limited precision, drift, and variability in device behavior, and the lack of general-purpose learning algorithms means most training still occurs offline using software models before deployment. The significance lies in pushing toward edge intelligence, where devices can learn continuously in real-time with minimal power, but practical, scalable solutions are still under active development.