Engineering
Why Quantum Tunneling Limits Transistor Scaling Below 3 Nanometers
Quick fact
At the 3-nanometer node, the gate oxide is so thin that electrons can quantum-tunnel through it, and the resulting leakage current would be so large that the transistor could not switch properly — threatening to end Moore's Law.
Why this is interesting
Your phone's processor once shrank by half every two years, but that ride is hitting a wall. Believe it or not, electrons are literally slipping through the transistors — and it's all because of quantum weirdness.
Read the full explanation
Understanding Why Quantum Tunneling Limits Transistor Scaling Below 3 Nanometers
To understand why quantum tunneling limits shrinking, imagine a transistor as a tiny switch that controls the flow of current. The switch has a gate electrode separated from the silicon channel by an insulating barrier, traditionally made of silicon dioxide. This barrier is incredibly thin — just a few atomic layers. In the everyday world, if you throw a ball at a wall, it bounces back. But in the quantum world, electrons behave like waves, and they have a small probability of simply appearing on the other side of the barrier — this is quantum tunneling. As the gate oxide gets thinner, that probability skyrockets. At around 3 nm thickness, so many electrons leak through that the transistor can no longer fully turn off, leading to wasted power and unreliable operation. This is why the classic scaling approach, which just shrinks everything proportionally, reaches a fundamental limit.
A deeper explanation
The mechanism is rooted in quantum mechanics. In a transistor, the gate oxide acts as a potential energy barrier for electrons in the channel. Classically, an electron with lower energy than the barrier height cannot cross. But because an electron also behaves as a wave, its wavefunction extends into the barrier. If the barrier is thin enough, there is a non-zero probability that the wavefunction 'leaks' through and the electron emerges on the other side. This probability increases exponentially as the barrier thickness decreases. In early nodes, using silicon dioxide, the oxide had to be made thinner to increase the transistor's speed and reduce its size. However, below about 3 nm, the tunneling leakage current becomes so large that it dominates the transistor's off-state current, making it impossible to maintain the on/off ratio required for digital logic. To mitigate this, chipmakers replaced silicon dioxide with high-κ dielectrics such as hafnium-based oxides, which have a higher dielectric constant, allowing a physically thicker layer that still provides the same capacitance (and thus gate control) while reducing tunneling. Additionally, new transistor architectures like finFETs and gate-all-around (GAA) improve electrostatic control, delaying the limit further. But the exponential nature of tunneling remains a hard barrier, pushing the industry toward new materials and device concepts beyond the 3-nm node.